MIPS ISA Emulator
Motivation
This was a small emulator project for learning what a processor simulator has to keep track of. The goal was not to make a fast SPIM replacement. It was to make the fetch, decode, and execute loop visible enough that I could understand how a hex instruction turns into register and memory changes.
The repo is intentionally simple: a Python file, a text file of hex instructions, and a data memory file. That made it easier to focus on the ISA logic instead of building a large tool around it.
Approach
The emulator loads 32-bit hex instructions from a text file into instruction memory, keeps a program counter, and stores register state in a 32-entry array. Each instruction is decoded by splitting out the opcode, register fields, function code, immediate value, and jump target.
The implementation supports a small but useful subset of MIPS: arithmetic, logical operations, shifts, comparisons, load/store, branches, and jumps. Memory is represented as Python lists, which keeps the behavior easy to inspect while testing.
- 32 general-purpose registers plus a program counter
- Separate instruction memory and data memory arrays
- R-type, I-type, and J-type decoding paths
- Support for
add,sub,and,or,nor,slt, shifts,lw,sw,beq,bne,j, andjal
Results
The most useful part was making state changes explicit. When something went wrong, I could print the registers, inspect the program counter, and compare the decoded fields against the instruction I expected.
It also made the awkward parts of ISA simulation more obvious. Branch offsets, jump targets, and memory addressing look simple in assembly, but they need clear rules once everything is encoded as bits.
References
- Patterson and Hennessy, Computer Organization and Design