MIPS ISA Emulator
title: "MIPS ISA Emulator" date: "2024-03-01" description: "A small MIPS instruction-set simulator with memory management." tech: ["C++", "MIPS"] status: "course-project" links:
- label: "GitHub" href: "https://github.com/amanpdesai/spimulator"
Motivation
Architecture courses tend to teach you what an ISA is without ever making you build something that interprets one. Writing an emulator forces you to confront the boring, load-bearing details: endianness, instruction encoding, the difference between a "register" in the textbook and a register in your data structures.
Approach
A trap-driven interpreter loop — fetch, decode, dispatch, execute. Memory is a flat byte array with a thin layer for word-level reads and writes. Hex-encoded program input gets parsed into the right MIPS instruction encoding before execution.
- Instruction decode by major opcode then function code
- Word-aligned memory accesses with explicit endian handling
- Minimal syscall surface for I/O
Results
Runs the standard set of small MIPS programs from the course. Probably the most direct way I've ever felt the gap between "I understand this on paper" and "I can implement it correctly."
What's next
- Add a pipeline simulator on top: fetch / decode / execute / memory / writeback as visible stages
- Cycle-accurate cache and branch-predictor models
References
- Patterson and Hennessy, Computer Organization and Design (the green book)